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pulled high). To initiate a data transfer, the master requesting the bus pulls down the SDA bus line, followed by the SCL bus line. During data transmission, this is an invalid condition because the data line is changing while the clock line is active/high. Each bit is then transmitted to or from the slave (the device the message is being communicated with by the master), with the negative clock edge being used to latch in the data, as shown in Fig. 17.44. To end data transmission, the reverse is executed; the clock line is allowed to go high, which is followed by the data line. Data is transmitted in a synchronous (clocked) fashion. The most signi cant bit is sent rst, and after 8 bits are sent, the master allows the data line to oat (it doesn t drive it low) while strobing the clock to allow the receiving device to pull the data line low as an acknowledgment that the data was received. After the acknowledge bit, both the clock and the data lines are pulled low in preparation for the next byte to be transmitted or a stop/start condition is put on the bus. Figure 17.45 shows the data waveform. Sometimes the acknowledge bit will be allowed to oat high, even though the data transfer has completed successfully. This is done to indicate that the data transfer has completed and the receiver (which is usually a slave device or a Master that is unable to initiate data transfer) can prepare for the next data request. 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There is a loose standard to use the most signi cant 4 bits to identify the type of device, whereas the next 3 bits are used to specify one of eight devices of this type (or further specify the device type). As I just said, this is loose standard. Some devices require certain patterns for the second 3 bits, whereas others (such as some large serial EEPROMS) use these bits to specify an address inside the device. In addition, there is a 10-bit address standard in which the rst 4 bits are all set, the next bit reset, and the last 2 bits are the most signi cant 2 bits of the address, with the nal 8 bits being sent in a following byte. All this means is that it is very important to map out the devices to be put on the bus and all their addresses. This is really all there is to I2C communication, except for a few points. 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